Q: How can i upgrade Kraken`s firmware ?

A: Simple. All You need is regular USB-C cable (good quality please!). Kraken has built in JTAG  USB bridge programmer. Do not buy any external programmer! NOT NEEDED !

WARNINGS: ( Thanks to Rene Egmond !)

• do not use any usb hubs! direct computer connection only
• use decent shortest possible usb c cables 
• disconnect all usb devices, that may interfere with jtagging ( all virtual com ports, other programmers, Arduino/Rasperry stuff,  etc. 
• to be sure all works, only mice/Keyboards shall be left.. 
• I know -  i am overreacting, but maybe it helps :-)

Just follow this  manual: https://lotharek.pl/files/Kraken/FPGA_FLASH.pdf

Q: Where can I download KRAKEN firmware ?

A: FILES tab above :-)

A: Phone/pc/mac with TAP/TZX player

Q: What are diffrence between SIZIF and Kraken ?

A: Very good question...Unfortunatelly, I do not have Sizif to compare directly, but along with KARABAS, ZX UNO and  Mist Core,  SIZIF was my big inspiration. I really do admire creators of above devices, but I wanted to have sth in between all of them. So, please find below my observations (judging from the schematic and pictures)

	SISIF 512	Kraken
Technology	THT in majority	SMD in majority
Main IC	CPLD	FPGA
Number of CPUS	1	2 - (fpga) + Z80
Number of AY	1 (2 with an extra addon card)	2 - (fpga)
Number of Saa1099	0 (1 real- extra addon card needed)	1 - (fpga)
Turbo Sound FM	0 (extra addon card needed)	YES - (fpga)
General Sound	0 (extra addon card needed)	possible, at the cost of TS FM and sof-core
RGB output	6 bit RGB	9 bit RGB
SoundDrive/COVOX	YES	YES
Built in games	NO	YES
Built in DIAGNOROM	?? YES	YES
OSD	SETUP	INFO (since 1.11 firmware)
Turbo	YES, needs 20mhz Z80	YES (soft core modes)
PWR SUPPLY	very wide range of power supplies, vey nice	needs 9-10V power supply, simplified but effcient
WI-FI HEADER	Yes	NO
BT HEADER	YES	YES
DivMMC	YES	NO
Joystick	YES	NO
Keybord HOT KEYS	NO - nice menu	YES
Can be built home	YES	NO /BGA/
Main IC firmware upgrade	NO, needed extra programmer	USB C FPGA flashing
PICTURE (CLICK)
Timex 2048 MODE	NO	YES (since 1.12 firmware)
RAM	512kB	512kB
CLOCK source	1 - 28MHz	2 - 28 Mhz / 28,3754 Mhz

Q: I WANT TO MAKE MY OWN VIDEO CABLE/WHAT IS PINOUT OF DIN9 ?

A: Sure. Please find it below:

The connector used by KRAKEN is very similar to  Sega Genesis (or Mega Drive) Model 2. Both sync/composite pins (4,5) ae  COMPOSISTE_SYNC connected  as different cables and adapters are known to use one or the other pin. Please, use only one of them. Make sure other stayes unconnected.

And..one more: 

            No extra elements needed inside cable

NO CAPS, NO RESISTORS

All elements needed are at KRAKENS PCB already 

Best effects one can obtain following direct scart connections :

HISTORY: (3 years at few pictures)

rev 1.0

rev 1.1A

rev 1.2 (2025-05-10)  - CODENAME "KRAKEN"

rev 1.3 

• reworked power supply
  • any power supply ranged 8-10V shall work
• minor dimensions/fitting holes corrections
• minor connectors positions corrections
• ULA PLUS video circuit from fpga added
• external clock, IORQ_E, Clock slector built on 1g chips ( in order to get extra pins from FPGA)
• added tackt switch to enable JTAG mode of fpga
• Dual purpose pins used to maximum ;-) (excpet reconfig_N) 
• dedicated port #FE octal bus tranciver added for Keybaord and TAPE_IN (yes..lack of pins in FPGA)
• many minor changes... to many to remeber ;-)

rev 1.4 - added AVR

rev 1.5 (a,b)

• fpga changed to bigger one
• rgb output reworked /9bit/
• keyboard controller reworked 
• many minor changes..

rev 1.5 c: - present version

• USB C fpga flash added
• minor pcb rework
• fpga rerouted - exscessive clock skews eliminated

Q. Tell me more about KRAKEN ?

This is a SystemVerilog/Verilog FPGA implementation of a ZX Spectrum computer, supporting multiple machine variants and a rich set of peripherals. The design targets an FPGA board (Rev B/C variants) with two clock inputs (28 MHz and 28.37516 MHz), external SRAM, a Z80 CPU socket, and analog video/audio outputs. The architecture is centered around a ULA (Uncommitted Logic Array) replacement that handles video generation, memory management, CPU clocking, I/O ports, and sound mixing — essentially everything the original Sinclair ULA did, plus significant enhancements.

Supported Machine Modes

The 3-bit MODE input selects one of 8 configurations:

Additionally, there is a Game Mode (activated by Symbol Shift + G) which forces a barebones 48K configuration with only beeper sound, intended for maximum compatibility with original software.

Module Architecture

Top Level: main (MAIN.sv)

The central integration module. It instantiates all subsystems, handles clock selection, configuration management, keyboard shortcut processing, reset logic, and the hardware/softcore Z80 bus multiplexing.

Key architectural decisions:

• The bus signals (A, D, IORQ_N, MREQ_N, etc.) are bidirectional — they can be driven by either an external Z80 chip or the internal T80 softcore, selected by Z80_FPGA_ENABLE.
• A cpu_bus SystemVerilog interface carries active-high registered versions of all CPU signals, sampled on negedge ZEGAR for consistent timing.
• Clock source is selected between CLK_INPUT0  and CLK_INPUT1 (28 MHz) based on MODE.

Clock & Timing: video 

The video module is the master timing generator. From the 28,XX  MHz master clock, it produces the entire clock hierarchy:

• clk14 (14 MHz), clk7 (7 MHz), clk35 (3.5 MHz) — derived from the horizontal counter hc0[0..2]
• ck14, ck7, ck35, ck175 — single-cycle clock enables for synchronous design
• clk12_5hz and lower — derived from a blink counter for cursor/flash timing

Timing parameters differ per machine (48K: 448 total H pixels, 312 lines; 128K: 456×311; Pentagon: 448×320), matching the original ULA timings.

CPU Controller: 

Handles CPU clock generation with contention emulation, turbo mode support, interrupt generation, and reset sequencing.

Contention model: Faithfully implements the original Spectrum memory contention — the CPU is stalled when accessing contended memory pages during specific horizontal counter phases. This is critical for software that relies on exact cycle timing (many games and demos do). Contention is disabled in turbo modes and on Pentagon.

Turbo modes: TURBO_7 runs the CPU at 7 MHz, TURBO_14 at 14 MHz. The turbo_wait mechanism ensures that memory and I/O accesses still take the correct number of cycles by inserting wait states.

INT generation: Machine-specific interrupt timing (48K: line 248 col 0; 128K: line 248 col 4; Pentagon: line 239 col 322). Interrupt length also varies.

Memory Management: 

The memory subsystem manages a shared external SRAM with prioriterized access between CPU, video, and ULAplus palette reads/writes.

Address mapping supports:

• Standard 128K banking (port_7ffd: 8 pages × 16KB in top 16KB)
• Pentagon 512K/1MB extensions (port_dffd)
• +3 special paging modes (port_1ffd: all-RAM configurations)
• Snow effect emulation (corrupted refresh address leaking into video reads)

RAM ACCES  priority:

1. CPU write (highest)
2. ULAplus write
3. CPU read
4. ULAplus read
5. Video read (lowest, can be preempted)

Video module:

Generates standard ZX Spectrum video output (256×192 active area with borders). Supports:

• Standard attributes: 8×8 character cells with ink/paper/bright/flash
• ULAplus mode: 64-color palette via external SRAM lookup (2 extra read steps per character cell for ink and paper palette entries)
• Composite sync output (active-low XOR of H and V sync)
• Floating bus emulation (port_ff_data) — returns the currently-being-read attribute or bitmap byte, as the original ULA did

The screen controller uses a 4-step read pipeline per character cell: attribute → bitmap → (ULAplus ink) → (ULAplus paper).

I/O Ports: ports 

Implements the classic Spectrum port decoding:

• Port #FE: Keyboard read (active-low matrix), border color write, beeper, tape I/O
• Port #7FFD: 128K memory paging (with lock bit 5 support and +3 compatibility)
• Port #1FFD: +3 special modes and disk motor control
• Port #DFFD: Pentagon extended RAM paging
• Ports #2FFD/#3FFD: +3DOS disk interface signals

ULAplus: 

Implements the ULAplus extended color mode via ports #BF3B (address register) and #FF3B (data). The palette is stored in external SRAM at a dedicated address range ({2'b00, 3'b111, 8'b11111111, 6-bit addr}), giving 64 palette entries with GRB332 color encoding.

Sound Subsystem

TurboSound: Dual AY-3-8912 PSG chips with registered address decoding and chip select via register #FF bit 0. All control signals are registered to improve timing. Generates 6 audio channels (A/B/C × 2 chips).

AY-3-8912: Full PSG implementation with envelope generator, noise generator, and I/O ports.

SAA1099 : Philips SAA1099 sound chip emulation (6 channels, stereo). Active on port #FF writes when enabled.

TwinFM / TSFM: Dual Yamaha YM2203 (OPN) FM synthesis chips using the jt03 core. Provides FM sound on left and right channels. Accessible via standard TurboSound-FM port addresses (#BFFD/#FFFD) with chip selection.

Covox & SounDrive: Simple 8-bit DAC interfaces. Covox on port #FB (mono, written to all 4 channels). SounDrive 1.05 on ports #0F, #1F, #4F, #5F (4-channel stereo).

Mixer : All audio sources are summed using 17-bit sigma-delta (1-bit) DACs:

• AY channels with stereo panning (Pentagon: ACB, others: ABC)
• Covox/SounDrive channels
• SAA1099 stereo
• YM2203 FM stereo (with DC offset correction: +32768)
• ULA sound (beeper + tape)
• Separate beeper DAC for the onboard speaker

Keyboard Scanner:

Implements an active keyboard matrix scanner that cycles through all 8 half-rows at a derived clock rate. The scanned state is stored in registers and combined based on the CPU's address lines (mimicking the original ULA's keyboard multiplexing). Special key combinations (Symbol Shift + letter) are detected for system functions.

Z80 Bus Arbiter: 

A 3-state FSM (BUS_OWNED → REQUESTING → BUS_FREE) that manages the transition between the external Z80 chip and the internal T80 softcore. When softcore mode is enabled, it asserts BUSRQ to the external Z80, waits for BUSAK, then takes over the bus.

ROM Controller: rom_control (ROM_controller.v)

Maps the ROM address lines based on machine type, Game Mode slot selection, and DiagnoROM mode. Supports up to 16 Game Mode ROM slots.

OSD: 

On-Screen Display overlay showing current mode/turbo status. Active briefly after reset and during key presses.

Beep Player: 

A small tune player (square wave sequencer) that plays a short jingle when turbo mode is activated. Plays a sequence of F4, F#4 notes with specific timing.